ReynoldsTech graciously donated a copperelectroplating tool to R.I.T., which speaks volumes and has far reaching potentials and challenges for, innovative research, patents and, incorporation of the damascene process into the thin film labs. Upon eventual integration into the classroom environment further designed experiments, process improvement and senior design projects, electroplating will eventually replace the existing aluminum metal layers with copper for the advanced 1.0 μm and O.5μm CMOS process currently used in the R.I.T. integrated circuit processing student run factory. From a ground zero approach with safety issues in mind the ramping up of this new tool had to be installed, a comprehensive manual rewritten, copper sulfate and sulfuric acid electrolyte chemicals added, then characterized and tested to determine its unique capabilities and deposition rates. The experiment used for gathering data incorporated the use of Faraday’s Law which states: “the amount of product formed is directly proportional to the charge passed” and “the mass of product formed is proportional to the electrochemical equivalent weight of the product.” Following in these footsteps for the theoretical values the ampere-minutes were varied and mass calculated and then compared against the actual mass values by measuring the mass of the wafer before and after plating. An actual thickness was determined and compared against the theoretical values that Faraday calculated.
Udut, Keith M.
"Electrolytic Plating of Copper,"
Journal of the Microelectronic Engineering Conference: Vol. 11
, Article 13.
Available at: https://scholarworks.rit.edu/ritamec/vol11/iss1/13