Silicon based ring gate surface junction tunneling devices (SJT) were studied due to their promise of incorporating quantum functional devices with integrated circuits. SJT devices of various gate lengths ranging from 1 μm to 50 μm were designed using Mentor Graphics tools, and were fabricated using standard CMOS processes on S1MOX substrates. SIMOX wafers were used to help reduce bulk leakage and enhance the drain impurity profile. SIMOX mesa isolation also significantly reduced the process flow.
Hughes, Eliott R.
"Design and Fabrication of Ring Gate Surface Junction Tunneling Devices,"
Journal of the Microelectronic Engineering Conference: Vol. 10
, Article 7.
Available at: https://scholarworks.rit.edu/ritamec/vol10/iss1/7