Description

Cryptographic S-boxes are fundamental in key-iterated sub- stitution permutation network (SPN) designs for block ciphers. As a natural way for realizing Shannon’s confusion and diffusion properties in cryptographic primitives through nonlinear and linear behavior, re- spectively, SPN designs served as the basis for the Advanced Encryption Standard and a variety of other block ciphers. In this work we present a methodology for minimizing the logic resources for n-bit affine-power S- boxes over Galois fields based on measurable security properties and find- ing corresponding area-efficient combinational implementations in hard- ware. Motivated by the potential need for new and larger S-boxes, we use our methodology to find area-optimized circuits for 8- and 16-bit S-boxes. Our methodology is capable of finding good upper bounds on the number of XOR and AND gate equivalents needed for these circuits, which can be further optimized using modern CAD tools.

Date of creation, presentation, or exhibit

9-30-2015

Comments

The final, published version of this paper was presented at the Military Communications Conference, MILCOM 2015, with the title "Constructing large S-boxes with area minimized implementations":

Wood, Christopher A.; Radziszowski, Stanislaw P.; Lukowiak, Marcin, "Constructing large S-boxes with area minimized implementations," in Military Communications Conference, MILCOM 2015 - 2015 IEEE, pp.49-54, 26-28 Oct. 2015 doi: 10.1109/MILCOM.2015.7357417

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Document Type

Conference Paper

Department, Program, or Center

Computer Science (GCCIS)

Campus

RIT – Main Campus

Download

Share

COinS