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Documents from 2006

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Evaluating Threat Assessment for Multi-Stage Cyber Attacks, Shanchieh Jay Yang, Jared Holsopple, and Moises Sudit

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Self-localization in ubiquitous computing using sensor fusion, Jeffrey Zampieron

Documents from 2005

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Modeling of a hardware VLSI placement system: Accelerating the Simulated Annealing algorithm, William Merle Batts Jr.

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RITSim: distributed systemC simulation, David Richard Cox

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A New Digital Image Compression Algorithm Based on Nonlinear Dynamical Systems, Chance Glenn, Michael Eastman, and Gaurav Paliwal

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Parts-based object detection using multiple views, David Higgs

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Hardware and Software Multi-precision Implementations of Cryptographic Algorithms, Muhammad A. Janjua

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Hardware Software Synthesis of a H.264 / AVC Baseline Profile Decoder, Stephen P. Joralemon

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Reconfigurable elliptic curve cryptography, Aarti Malik

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Data Aggregation and Cross-layer Design in WSNs, Carter May

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A new design methodology for mixed level and mixed signal simulation using PSpice A/D and VHDL, Sreeram Rajagopalan

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Vision-based hand shape identification for sign language recognition, Jonathan Rupe

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SPECTRA: Secure Power Efficient Clustered Topology Routing Algorithm, Waqaas Siddiqui

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Linux OS emulator and an application binary loader for a high performance microarchitecture simulator, Scott Warner

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VHDL Modeling of an H.264/AVC Video Decoder, Thomas Benjamin Warsaw

Documents from 2004

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Support Vector Machines in a real time tracking architecture, Benjamin Castaneda

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Genetic algorithms in cryptography, Bethany Delman

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Performance estimation techniques for micro-heterogeneous computing systems, Mikhail Goltsman

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Concurrent evolution of feature extractors and modular artificial neural networks, Victor Hannak

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Image sequence restoration by median filtering, Shawn R. Jackson

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Multiprocessor DSP Implementation of the JPEG 2000 Codec, Scott Mayne

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Feasibility analysis of correlation based prefetching using digital signal processing, David L. Morse

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Evaluation of the PlayStation 2 as a cluster computing node, Christopher R. Nigro

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A Convex Optimization Approach to the Design of Multiobjective Discrete Time Systems, Anirudh Oberoi

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Statistical closed-loop process scheduling, James D. Remus

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VHDL implementation and synthesis of adaptive thresholding, Nicholas P. Sardino

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Efficient Human Facial Pose Estimation, James C. Schimmel

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Linux kernel support for Micro-Heterogeneous Computing, Kim R. Schuttenberg

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Optimal Topologies for Wireless Sensor Networks, Jason Tillett, Shanchieh Jay Yang, Raghuveer Rao, and Ferat Sahin

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Developing an example-based faculty training course, Anthony Trippe and Karen Vignare

Documents from 2003

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A flexible hardware architecture for 2-D discrete wavelet transform: design and FPGA implementation, Richard Carbone

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0.18 µm CMOS low power standard cell library, Suryadi Gunawan

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Preserving conformance for GCRA regulated flows, Deryck Hong

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Near-Lossless Bitonal Image Compression System, Jeremy Pyle

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Improved methods and system for watermarking halftone images, Phil Sherry

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Media processor implementations of image rendering algorithms, Josephine Smith

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An Exploration of MPEG-7 Shape Descriptors, Bret Woz

Documents from 2002

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Analysis of H/W & S/W techniques for data reduction in high speed digital image processing, Paul DeSanctis

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Analysis and hardware implementation of color map inversion algorithms, Michael Martin

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An Investigation of trace cache organizations for superscalar processors, Edward Mulrane Jr

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Simultaneous multithreading: Operating system perspective, Vyacheslav Rubinfine

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Efficient Utilization of Fine-Grained Parallelism using a microHeterogeneous Environment, William L. Scheidel

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Reconstructing the Boundary of a Web Document, James Sweet

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Support vector machines for image and electronic mail classification, Matthew Woitaszek

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A Parallel implementation of an mpeg-2 encoder using message-passing, Jennifer Zenner

Documents from 2001

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Firewall strategies using network processors, Matthew Mariani

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Adaptive virtual protocol stacks for intrusion detection applications, David McGann

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Hardware Implementation of JPEG-LS codec, Michael Piorun

Documents from 2000

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An Evaluation of the S2Ia switched-current architecture for (delta)(sigma) modulator ADCs, Andre Botha

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A VHDL design for hardware assistance of fractal image compression, Andrew Erickson

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Digital image watermarking techniques, Christopher Martin

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The Design, modeling and simulation of switching fabrics: For an ATM network switch, Dmitriy Molokov

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An Investigation of thread scheduling heuristics for a simultaneous multithreaded processor, Ralph Zajac Jr

Documents from 1999

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Guaranteed bandwidth implementation of message passing interface on workstation clusters, Ali Atalay

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The Comparison of three 3D graphics raster processors and the design of another, Paul Brown

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Server selection for mobile agent migration, Wayne Caro

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Behavior synthesis for high speed 3D color interpolation using VHDL, Thomas Glanville Jr

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Asynchronous circuit simulation and design methodologies, Michael Hevery

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Self-Similarity in a multi-stage queueing ATM switch fabric, Adam Lange-Pearson

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Investigation of a simultaneous multithreaded architecture, Marc Torrant

Documents from 1998

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The Effects of the architectural design, replacement algorithm, and size parameters of cache memory in uniprocessor computer systems, Eric Berzofsky

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Exploring design patterns with the Java programming language, Stephanie Burton

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A Shared memory multiprocessor system architecture utilizing a uniform, Frank Casilio

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Real-Time Implementation of JPEG Encoder/Decoder, Thomas M. Czyszczon, Roy S. Czernikowski, Muhammad Shaaban, and Kenneth Hsu

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An Approach to remote process monitoring and control, John Dracos

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Design and implementation of a DSP based MPEG-1 audio encoder, Eric Hoekstra

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Evolving hardware with genetic algorithms, Kevin Kerr

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Lempel Ziv Welch data compression using associative processing as an enabling technology for real time application, Manish Narang

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Coarse-grained parallel genetic algorithms: Three implementations and their analysis, Daniel Pedersen

Documents from 1997

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An Investigation and evaluation of promela/spin as a validation tool for asynchronous concurrent systems, Mark Bezdany

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Java based location independent desktop environment, Jeffrey Harman

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An Experimental analysis of the MPEG compression standard with respect to processing requirements, compression ratio, and image quality, Daniel Howard

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Design and evaluation of multimedia extensions for the DLX architecture, Brian Hughes

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A Morphological array image processor controller chip set, Christopher Insalaco

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A Java based internet file system service, Keith Miller

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The Design and modeling of input and output modules for an ATM network switch, Darin Murphy

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VHDL design of a DES encryption cracking system, Thomas Oelke

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Evolution of solutions to real-time problems, Greg Semeraro

Documents from 1996

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A Buffering strategy for stabilizing network data rates, Brian Bell

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A Petri net design, simulation, and verification tool, Richard Brink

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Implementation of a real-time industrial web scanning system hardware architecture, Lowell Ferguson

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A VHDL model of a superscalar implementation of the DLX instruction set architcture, Paul Ferno

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Super scalar high speed 2(mew) N-well MOSIS CMOS digital halftoning processor, Anupam Gupta

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VHDL implementation of an image processing chip, E. Michael Kelly

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A Performance evaluation of several ATM switching architectures, Jeffrey Krieger

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Boundary scan system design, Craig Loomis

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The Design of a single chip 8x8 ATM switch in 0.5 micrometers CMOS VLSI, Rudi Rughoonundon

Documents from 1995

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A VHDL model of a digi-neocognitron neural network for VLSI, Troy Brewster

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Statistical SPICE parameter extraction for an n-well CMOS process, Scott Hildreth

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ASIC design of an IIR digital filter: Using Mentor Graphics DSP Station Tools, Robert Panek

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Features and neural net recognition strategies for hand printed digits, Jeffrey R. Pink

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Implementation of fractal image coding, Peter Stubler

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Characterization of digital film scanner systems for use with digital scene algorithms, Mark Vernacotola

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Simulation of a neural network-driven fuzzy controller, Karl Ver Schneider

Documents from 1994

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A Flexible development system for stepper motor based electro-mechanical subassembly design, Joseph Baco

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A VHDL design of a JPEG still image compression standard decoder, Douglas Carpenter

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A High speed 16-bit RISC processor chip, Wan-Fu Chen

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Fuzzy approach for Arabic character recognition, Adnan El-Nasan

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VHDL modeling and design of an asynchronous version of the MIPS R30000 microprocessor, Paul Fanelli

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Heuristics for selecting gray scale morphological structuring elements, Paul Fetter