Abstract

Processors and embedded systems perform algebraic manipulations such as addition, subtraction, multiplication and division on integers in order to complete and execute programs. Unfortunately, most division cores in these devices take significantly more time to compute than other manipulations. Because of this, research has been conducted on finding a division algorithm that does not take as long to execute. This graduate paper discuses and proposes a division core design based on ancient Vedic mathematics. The design is created and simulated as a 4-bit system for completion and analyzed for timing, power consumption, and cell area usage. Estimations on larger designs are completed and used to compare this design to similar ones. It is found that the timing and cell area usage are very minimal compared to other designs based on the same algorithm. However, the power consumption is significantly higher. Possible optimizations and improvements to the design are proposed for future use. At the end of this graduate paper, recommendations are given to optimize and upgrade the current design.

Publication Date

5-2017

Document Type

Master's Project

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Mark A. Indovina

Advisor/Committee Member

Sohail A. Dianat

Campus

RIT – Main Campus

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