Abstract

Silicon Photonics is a promising new technology for realizing efficient, high performance interconnects. There is a growing need for educating future engineers on how to design, fabricate, package and test silicon photonic circuits. Silicon photonic processing for an educational institution with i-line lithography capabilities is demonstrated and the thesis elaborates on the fabrication process used for realizing passive photonic devices and circuits (i.e. waveguides, interferometric structures and fiber chip grating couplers). The process is realized in a CMOS compatible environment which has been in use since 1986 to teach microelectronic engineering. And is now also being used to support the AIM Photonics Academy education mission. Specifically, TM-polarized grating coupler with a ring resonator, y-branch, bidirectional coupler and three-way couplers were fabricated with a lithographic resolution of less than 400 nm on an SOI wafer. The setup time and run time required was 3 days in comparison to the long wait time in the industry. Optimization of the resolution using ARC i-CON7, diluted OiR 620 and the etch selectivity of the silicon to the 1:1 OiR 620: PGMEA is key to the student run fabrication process. Alternatives for the hard mask used for etching and other plasma etch tool alternatives were explored and is supported by the Optical microscope and SEM results. The pattern fidelity of the Y splitter was simulated using PROLITH and the design was imported into Lumerical FDTD. The test results of the photonic circuits fabricated were analyzed and compared with the Lumerical FDTD and Lumerical INTERCONNECT simulations.

Publication Date

7-28-2017

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Stefan F Preble

Advisor/Committee Member

Dale Ewbank

Advisor/Committee Member

Robert Pearson

Campus

RIT – Main Campus

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