Abstract

Amorphous oxide semiconductors (AOS) have been extensively studied for their application in thin-film electronics; an area which is currently dominated by hydrogenated amorphous silicon (a Si:H) technology. Indium-gallium-zinc oxide (IGZO) has garnered most of the AOS materials focus due to its high carrier mobility and process simplicity. When modifying an existing process flow for fabrication of TFTs, the effect of each modification on the electrical characteristics must be determined. The compatibility of the process with the constraints of a glass substrate must also be considered. A new test chip layout was created that enables the fabrication of TFTs with a variety of electrode configurations including top-gate, bottom-gate, double-gate, and either staggered or co-planar source/drain regions. TFTs were fabricated on glass and oxidized silicon substrates, consisting of sputter-deposited IGZO surrounded by SiO2 dielectric layers, an oxidizing ambient anneal treatment, and a capping layer deposited by atomic layer deposition (ALD). Electrical characteristics from each process treatment and gate configuration were compared, with some noted differences in device operation related to process integration. A SPICE level 2 compatible IGZO TFT model was developed, with extracted parameter values providing quantitative measures for comparison.

Publication Date

8-2-2017

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Karl Hirschman

Advisor/Committee Member

James Moon

Advisor/Committee Member

Robert Pearson

Campus

RIT – Main Campus

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