Abstract

In recent years, many technologies have come forward to address the display industry’s increasing demand for improved TFT performance over a-Si:H. Low Temperature Polycrystalline Silicon (LTPS) is one such material which has been extensively researched due to its high mobility and high TFT current drive. Flash Lamp Annealing (FLA) is a technique which is potentially capable of forming LTPS on large glass substrates, thus reducing cost and increasing throughput compared to raster-scan Excimer Laser Annealing (ELA) which is inherently slow and relatively complex. Polycrystalline silicon with grain size of 10’s of microns has been shown using this technique. NMOS and PMOS TFTs with a top gate coplanar structure have been fabricated on display glass which showed very promising results as described below. A SiO2 capping layer was deposited on etched a-Si mesas, which was then used as screen oxide for source/drain ion implantation. Substrate heating at 525°C was implemented to reduce thermal loss during the FLA exposure. The implanted a-Si mesas were FLA exposed with 20 kW/cm2 power for 250 µsec, which yielded large-grain size. The TFTs fabricated had a best-case channel mobility of 380 cm2/V-sec and 143 cm2/V-secs for NMOS and PMOS, respectively. This work presents the first demonstration of CMOS TFTs using the FLA process.

Library of Congress Subject Headings

Tunnel field-effect transistors; Annealing of crystals

Publication Date

12-2016

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Karl Hirschman

Advisor/Committee Member

Robert Pearson

Advisor/Committee Member

Denis Cormier

Comments

This thesis is embargoed until 12/17.

Physical copy available from the Wallace Library at TK7871.95 .B43 2016

Campus

RIT – Main Campus

Plan Codes

EEEE-MS

Available for download on Wednesday, December 20, 2017

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