A 100 nm CMOS process is modeled and simulated using advanced ion implantation, diffusion models, recombination and mobility models; in ATHENA and ATLAS respectively. This process is designed for a mask length of 150 nm and effective gate length of =
The drive current on modeled and simulated device for NMOS and PMOS are 300 µA/µm and 63 µA/µm at 1.2 V drain and gate bias respectively. The threshold voltage for the modeled NMOS and PMOS is 0.479 V and -0.58 V with DIBL less than 12 mV/V on both the devices.
Unit process improvements includes retrograde well doping to reduce short channel effects, double exposure to obtain minimum feature size, anisotropic polysilicon and nitride spacers etch, high dose source drain extension implants to minimize the contribution of parasitic resistance to ON state performance of the device, high dose source drain implants followed by SALICIDE process to provide ohmic contacts. Fabricated devices failed because of excessive gate leakage.
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary--Design and construction; High performance processors--Design and construction; Low voltage integrated circuits--Design and construction
Electrical Engineering (MS)
Department, Program, or Center
Electrical Engineering (KGCOE)
Lynn F. Fuller
Karl D. Hirschman
Amareshbabu, Chandan K., "Modeling, Simulation and Fabrication of 100 nm (Leff) High Performance CMOS Transistors" (2014). Thesis. Rochester Institute of Technology. Accessed from
RIT – Main Campus