Abstract

In the deep submicron range of integrated circuit design, interconnects and not the logical gates are causing the performance bottleneck. The number of available transistors increase by a factor of 2 every technology node but interconnects do not scale with devices, devices scale down faster and thus the present designs need to be scalable and reusable. Pipeline interconnect free (PIF) logic methodology has a potential to solve these current design problems. In PIF logic methodology the global interconnects are replaced by a chain of logical gates. PIF logic uses only one type of gate which can be connected only to the adjacent eight gates making the gate and the interconnect modeling easier. In order to migrate from one technology node to other, just one PIF cell needs to be redesigned. The PIF cell in new technology node can replace the present cells thus making PIF logic based circuits fully reusable. This thesis implements PIF design methodology to develop two libraries consisting of combinational and sequential functional blocks such as adder, shift registers, multiplexers, decoders and encoders. The performance of these functional blocks is compared with the standard cell implementation with respect to the quality metrics (power dissipation, propagation delay and layout area).

Publication Date

1-2005

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Dorin Patru

Advisor/Committee Member

P. R. Mukund

Advisor/Committee Member

James Moon

Campus

RIT – Main Campus

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