Continuous advancements in devices, materials and processes have resulted in integrated circuits with smaller device dimensions, higher functionality and higher speed. The complementary metal oxide semiconductor (CMOS) technology has been the engine of this success. The MOS transistor is shrinking following the Moore's Law over the last several decades. As the device dimensions are approaching nanometer regime, parasitic resistance, capacitance and inductance are beginning to influence the performance significantly.
Self-aligned silicide process was developed in mid eighties that allowed reduction of gate and contact resistance by using metal silicides as low resistivity materials. The process also enabled higher packing density.
Many silicides have been extensively studied and Titanium silicide (TiSi2) and Cobalt silicide (CoSi2) have been implemented into modern devices. With devices shrinking, TiSi2 and CoSi2 are finding serious limitations of linewidth effect and excessive silicon consumption. One attractive alternative is nickel monosilicide (NiSi). NiSi has comparable resistivity as traditional silicides yet consumes less silicon during formation, no line width dependence, single thermal treatment, and relatively planar silicide-silicon interface. However, implementation of NiSi into future generation devices has been delayed by limited knowledge of its thermal instability.
In the study presented in this thesis, silicidation of nickel metal has been investigated. Silicidation has been carried out on doped and non-doped polycrystalline and crystalline silicon regions. Rapid thermal process was used for the silicidation of sputtered nickel metal into nickel silicide. The electrical and material properties of nickel silicide were characterized, and correlations between electrical data, material properties, and silicidation conditions have been made.
Electrical resistivity was calculated through the uses of sheet resistivity measurements using the four-point probe technique and the grooving technique. The grooving technique was used to measure the silicide's thickness necessary for electrical resistivity calculation. The silicide surface topography and phase composition were analyzed using the AFM and XRD technique respectively. Furthermore, RBS and SIMS analysis were done to complement the material properties study of nickel silicide.
The experimental result showed strong correlation between nickel silicide's electrical resistivity with surface topography and phase composition. A multiple phases mixture composition was observed in crystalline silicon and polysilicon regions at temperature less than 573°C and 695°C respectively. It is concluded that the most optimal silicidation condition for obtaining the single-phase nickel monosilicide was at 695°c for 60 sec. Such condition yield a NiSi film with an electrical resistivity of ~1.6 x 10-5 (Si), 3.3 x 10-5 Ω-cm (Poly). The most optimal silicidation for obtaining the lowest multi-phase mixture silicide was found to be at 500°C for 20sec or more. Such condition yielded a NixSi + NiSi phase mixture with an electrical resistivity of ~ 1.6 x 10-5 (Si), 2.5 x 10-5 Ω-cm (Poly).
Library of Congress Subject Headings
Integrated circuits--Materials; Silicides; Nickel compounds
Materials Science and Engineering (MS)
Department, Program, or Center
Center for Materials Science and Engineering
Sean L. Rommel
Surendra K. Gupta
Do, Phu H., "Development of nickel silicide for integrated circuit technology" (2006). Thesis. Rochester Institute of Technology. Accessed from
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