Abstract

The predominant integrated circuit fabrication technologies used for VLSI devices are CMOS, and BiCMOS. The goal of this work was to develop a CMOS process that could be converted into a BiCMOS technology. For this reason an N-Well CMOS process was selected, and fabricated in the Microelectronic Engineering clean room. This paper reviews the test chip design, process simulation, fabrication, and electrical characterization of this process. The device fabrication was successful, and the electrical testing clearly indicated what measures need to be taken to improve the process.

Library of Congress Subject Headings

Metal oxide semiconductors, Complementary

Publication Date

11-1-1992

Document Type

Thesis

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Fuller, Lynn

Advisor/Committee Member

Pearson, Robert

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.99.M44 P74 1992

Campus

RIT – Main Campus

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