A procedure for determining process control and yield prediction is presented which primarily serves to evaluate the quality and repeatability of critical fabrication steps, but also serves to quantify process capabilities and limitations for future design considerations. This can be accomplished through the use of a specially designed test chip. The test chip is designed for use in determining the process control and fabrication capability of the Microelectronic Engineering Department's fabrication lab of Rochester Institute of Technology.
Library of Congress Subject Headings
Process control--Technological innovations--Testing; ntegrated circuits--Design and construction
Department, Program, or Center
Electrical Engineering (KGCOE)
Meisenzahl, Eric J., "A Test chip approach to routine process control" (1988). Thesis. Rochester Institute of Technology. Accessed from
RIT – Main Campus