Abstract
A procedure for determining process control and yield prediction is presented which primarily serves to evaluate the quality and repeatability of critical fabrication steps, but also serves to quantify process capabilities and limitations for future design considerations. This can be accomplished through the use of a specially designed test chip. The test chip is designed for use in determining the process control and fabrication capability of the Microelectronic Engineering Department's fabrication lab of Rochester Institute of Technology.
Library of Congress Subject Headings
Process control--Technological innovations--Testing; ntegrated circuits--Design and construction
Publication Date
3-1-1988
Document Type
Thesis
Department, Program, or Center
Electrical Engineering (KGCOE)
Advisor
Fuller, Lynn
Advisor/Committee Member
Turkman, R.
Advisor/Committee Member
Ramanan, S.
Recommended Citation
Meisenzahl, Eric J., "A Test chip approach to routine process control" (1988). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/5564
Campus
RIT – Main Campus
Comments
Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TS156.8.M43 1988