Paul Ferno

Abstract

The complexity of today's microprocessors demands that designers have an extensive knowledge of superscalar design techniques; this knowledge is difficult to acquire outside of a professional design team. Presently, there are a limited number of adequate resources available for the student, both in textual and model form. The limited number of options available emphasizes the need for more models and simulators, allowing students the opportunity to learn more about superscalar designs prior to entering the work force. This thesis details the design and implementation of a superscalar version of the DLX instruction set architecture in behavioral VHDL. The branch prediction strategy, instruction issue model, and hazard avoidance techniques are all issues critical to superscalar processor design and are studied in this thesis. Preliminary test results demonstrate that the performance advantage of the superscalar processor is applicable even to short test sequences. Initial findings have shown a performance improvement of 26% to 57% for instruction sequences under 150 instructions.

Library of Congress Subject Headings

Microprocessors--Design and construction--Computer simulation; RISC microprocessors; VHDL (Computer hardware description language)

Publication Date

10-1-1996

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Shank, Kevin

Advisor/Committee Member

Chang, Tony

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7895.M5 F476 1996

Campus

RIT – Main Campus

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