Paul Fanelli

Abstract

The goal of this thesis is to demonstrate the feasibility of converting a synchronous general purpose microprocessor design into one using an asynchronous methodology. This thesis is one of three parts that details the entire design of an asynchronous version of the MIPS R3000 microprocessor. The design includes the main architectural features of the R3000: the 5-stage pipeline, the thirty-two 32-bit register bank, and the 32-bit address and data paths. To limit the size of the project, the memory and coprocessor are excluded. Therefore, this design has implemented the entire set of instructions from the original synchronous version with the exception of the coprocessor support instructions. The three participants in this project are Paul Fanelli, Kevin Johnson, and Scott Siers. Paul Fanelli developed the Very High Speed Integrated Circuit Hardware Description Language (VHDL) models for the processor. Three models, behavioral, dataflow, and structural, were constructed. Kevin Johnson designed the register bank, the arithmetic logic unit, and the shifter, including schematic diagrams and layouts. Scott Siers designed the pipeline stages, the multiplier/divider, the exception handler, and the completion signal generator, including schematic diagrams and layout. Each of the participants has written a separate thesis that covers one part of the total design.

Library of Congress Subject Headings

MIPS R3000 series microprocessors--Computer simulation; VHDL (Computer hardware description language); Computer architecture

Publication Date

2-1-1994

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Brown, George

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.8.M522F36 1994

Campus

RIT – Main Campus

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