Abstract
Very high speed integrated circuit Hardware Description Language (VHDL) is utilized in this project to model a Morphological Image Processor (MIP) Array. Both behavioral and structural models have been established at the system level, and the simulation results from both models are consistent with each other. The successful implementation of the models accomplishes our original goal to document the MIP with VHDL. It is observed from the project that VHDL is a powerful language. It is flexible since it can be used to model any level of a system independent of the technology.
Library of Congress Subject Headings
Image processing--Digital techniques--Mathematics; Morphisms (Mathematics); VHDL (Computer hardware description language); Digital filters (Mathematics)
Publication Date
2-1-1993
Document Type
Thesis
Department, Program, or Center
Computer Engineering (KGCOE)
Advisor
Brown, George
Advisor/Committee Member
Chang, Tony
Advisor/Committee Member
Czernikowski, Roy
Recommended Citation
Chen, Hao, "Simulation of a morphological image processor using VHDL - Part II: Control Mechanism" (1993). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/4609
Campus
RIT – Main Campus
Comments
Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TA1632.C464 1993