Abstract

The design and implementation cycle of an 8 bit CMOS microprocessor is discussed. The primary steps in the design procedure of the microprocessor consists of instruction selection, instruction encoding and organizational specification. A simple architecture is chosen to allow the emphasis of this investigation is focused upon the entire design procedure, Software behavioral models of functional blocks within the processor are used to validate the architecture. The functional blocks are then replaced with logic circuit models and tested. After logical simulations of all blocks have been completed, physical simulations of the logic circuits are performed using a SPICE like simulator to extract delay characteristics of longest circuit paths. Using this delay information, a preliminary estimate of processor speed is possible. Layout of the processor is generated using the Department of Computer Engineering's 2 uM CMOS Standard Cell Library.

Library of Congress Subject Headings

Microprocessors--Design and construction; Metal oxide semiconductors, Complementary

Publication Date

6-1-1992

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Brown, George

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7895.M5C67 1992

Campus

RIT – Main Campus

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