Digital halftoning is the algorithmic process for converting electronic images into bitonal images that preserves the perception of a continuous-tone image. Various digital halftoning algorithms were considered in the development of this processor on the basis of quality of image and amenability for VLSI implementation. An error-diffusion algorithm with the options of noise encoding, printer model adjustment, and edge enhancement was chosen for implementation. Since the algorithm allows for multiple independent parallel processors to operate on the same image, the system is capable of super scalar processing. The processor is intended for an 8-bit input (256 gray levels). The processor was designed using a 2\x. N-well MOSIS CMOS process. The expected processor speed for that process is about 21 million pixels/sec. The processing speed was enhanced by using Double Pass Transistor Logic implementation on all logic components used in the processor.
Library of Congress Subject Headings
Image processing--Digital techniques; Computer graphics
Department, Program, or Center
Computer Engineering (KGCOE)
Gupta, Anupam, "Super scalar high speed 2(mew) N-well MOSIS CMOS digital halftoning processor" (1996). Thesis. Rochester Institute of Technology. Accessed from
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