A new computer architecture, intended for implementation in late and post silicon technologies, is proposed. The architecture is a fine-grained, inherently parallel system consisting of a large grid of thousands or millions of simple "atomic processors" (APs) employing a simple instruction set. Each AP is configured as either a program instruction or data storage element. These elements are organized into logical entities, analogous to traditional programming functions/methods and data structures. Programming work is underway to compile and run programs from traditional sequential code where parallelism is automatically discovered at the high level on both instruction level and function level, and integrated into the object code that is then sent to the processor. The result is a massively parallel architecture that fully exploits instruction and thread-level parallelism. The architecture design is presented, in-progress work involving conversion of existing code is discussed, and examples are shown to indicate the speedup potential that exists in this new architecture when compared to current architectures.
Library of Congress Subject Headings
Computer architecture--Design; Parallel programming (Computer science); Parallel processing (Electronic computers); Multiprocessors
Spirer, Adam, "Pond: A Robust, scalable, massively parallel computer architecture" (2010). Thesis. Rochester Institute of Technology. Accessed from
RIT – Main Campus