Eric Ernst

Abstract

Due to significant bit-rate savings and improved perceptual quality, H.264/AVC, the latest video compression standard from the Joint Video Team, is receiving widespread adoption. Greater coding efficiency relative to previous standards is a result of additional techniques and features. One important change is the inclusion of an in-loop deblocking filter for removal of blocking artifacts. Since the filter can easily account for one-third of the computational complexity of a decoder, its addition was a source of debate during the development of the H.264/AVC standard. Ample research on architecture design of the deblocking filter has been carried out, generally targeted toward high performance profiles. To the best of our knowledge no other research investigated designs that can be scaled from low-power extended profiles up to high performance profiles. This work investigated the design of a scalable architecture for the deblocking filter. Four different designs were implemented. The relative performance of the designs were then compared against each other and existing research through simulation. All designs were targeted towards a Xilinx Virtex 5 field programmable gate array (FPGA).

Library of Congress Subject Headings

Electric filters, Digital--Design and construction; Imaging systems--Image quality; Video compression standards--Data processing; Decoders (Electronics)--Design and construction

Publication Date

7-1-2007

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Lukowiak, Marcin

Advisor/Committee Member

Savakis, Andreas

Advisor/Committee Member

Kudithipudi, Dhireesha

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7872.F5 E76 2007

Campus

RIT – Main Campus

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