Thomas Oelke

Abstract

This thesis illustrates the design of a chip to crack a message encrypted with Digital Encryption Standard (DES). VHSIC Hardware Description Language (VHDL) is used to describe the system. Part of the design criteria of the system is to provide a scalable and reconfigurable set of DES building blocks in VHDL. In order to provide this, a modular design with a pipeline architecture is employed. This system could be synthesized to produce actual hardware in either an ASIC or FPGA part. Simulations using Synopsys with Actel's 3200DX FPGA library demonstrate that the design could be run at over 16Mhz. Because a pipelined architecture is employed which retires one key every clock cycle the chip would be able to test over 1 6 million keys per second. This is a vast improvement over current software-only based approaches that achieve speeds of 1 to 2 million keys per second on expensive high-end micro-processors.

Library of Congress Subject Headings

Computer security--Research; Computers--Access control--Research; Data encryption (Computer science)--Research; Cryptography--Research; VHDL (Computer hardware description language)

Publication Date

6-1-1997

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Czernikowski, Roy

Advisor/Committee Member

Shaaban, Muhammad

Advisor/Committee Member

Hsu, Kenneth

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.9.A25 O44 1997

Campus

RIT – Main Campus

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