MOS capacitors and NMOS transistors were fabricated with various gate oxides and inter- level dielectrics (ILDs) in order to study the effects of plasma induced charging during the post-metal plasma deposition of an insulating oxide layer. The gate oxides investigated include thermal SiO 2, a low temperature oxide (LTO) deposited by low pressure chemical vapor deposition (LPCVD) using silane and oxygen, and an oxide deposited by plasma enhanced chemical vapor deposition (PECVD) using tetra-ethylortho- silicate (TEOS) as a precursor. A standard-recipe TEOS-based ILD was studied, as well as an alternative recipe that utilized decreased power. Additional wafers were fabricated with an LTO ILD to serve as a control group in order to isolate the influence of the ILD deposition on the respective gate dielectric. By studying C-V and I-V characteristics, both interfacial degradation as well as bulk charging was demonstrated as a result of the PECVD ILD deposition. The investigation demonstrated clear differences in plasma- induced charge effects on the various gate dielectrics. A correlation between the ILD deposition power and the resulting charge influence was established. In addition, post-plasma annealing experiments were done to study the thermal stability of induced charge.
Library of Congress Subject Headings
Metal oxide semiconductors--Research; Gate array circuits; Semiconductors--Defects; Dielectric devices; Plasma radiation
Department, Program, or Center
Center for Materials Science and Engineering
Mulfinger, Robert, "Investigation of induced charge damage on self-aligned metal-gate MOS devices" (2006). Thesis. Rochester Institute of Technology. Accessed from
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