Investigation of sputtered hafnium oxides for gate dielectric applications in integrated circuits
Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7872.D53 .J34 2006
Abstract
This work investigated high permitivity hafnium based dielectric films for use in future generation metal oxide semiconductor field-effect transistor (MOSFET) technologies. For the sub-100 nm MOS structure, the conventional SiO2 gate dielectric required is becoming too thin (<1.2 nm). The extremely thin silicon dioxide gate dielectric can no longer prevent tunneling current. The International Technology Roadmap for Semiconductors (ITRS) has identified the need for the “introduction and process integration of high-k gate stack materials and processes for high performance, low operating and low standby power MOSFETs.” Hafnium based oxides have shown great promise as gate dielectric materials, and are a prime candidate to replace silicon dioxide. Two deposition processes were used for investigating hafnium oxide: A traditional reactive sputtering process using a hafnium target and oxygen along with a metal oxidation process in which hafnium metal was deposited and subsequently oxidized in a rapid thermal processor. The films and their interfacial layers were studied using transmission electron microscopy and Rutherford backscattering. Suppression of the interfacial layers was attempted by utilizing various pre-deposition cleaning processes, nitrogen incorporation, and multiple annealing conditions. Statistical analysis was performed on many film properties including: thickness and refractive index by ellipsometry, equivalent oxide thickness (EOT), relative permittivity (εr), total charge density (NSS) via capacitance-voltage analysis (C-V), oxide charge density (QOX) and interface trap charge density (DIT) from surface charge analysis, and breakdown strength vii and leakage current density from current-voltage analysis (I-V). Hafnium oxide was successfully integrated into an RIT sub-micron NMOS process, and operational 0.5 μm transistors were fabricated and tested.
