Publication Date
1997
Document Type
Paper
Abstract
A self-aligned twin-well process has been developed for RIT’s Student CMOS Factory. These wells are self-aligned providing increased packing density; which, will allow for increased speed and reduction in defectively levels. In addition the twin-well process offers: decreased Early effect, increased punchthrough voltage and, reduced latch-up susceptibility, for those devices normally manufactured in substrate. Standard RIT Student Factory CMOS implements a p-well process. Four micron by 32 micron p-channel devices were tested to determine process performance. Early voltage was increased from 9.4V for p-well, to 38.8V for twin-well CMOS. Punchthrough voltage was increased in magnitude from 8V for p-well to 12V for twin-well. Saturation current at 5V Vds and 2.5V above Vt dropped in magnitude from 151μA/μm for p-well to 81μA/μm for twin-well.
Recommended Citation
Gendron, Kenneth A.
(1997)
"Twin-Well CMOS Integration,"
Journal of the Microelectronic Engineering Conference: Vol. 8:
Iss.
1, Article 1.
Available at:
https://repository.rit.edu/ritamec/vol8/iss1/1