A single-mask self aligned Twin-well process has been integrated into RIT’s CMOS technology. These wells are self aligned to increase package density. The process has been simulated using TMA Suprem IV simulation tool. The simulated parameters were used in the actual fabrication. The wells are used to optimize both n- and p-channel active devices. The subthreshold leakage currents in isolated pmos and nmos devices are -1.28 pA.4/μn and 3.56 nA/μm of channel width, respectively when the devices were biased at < 5 volts. In addition, the twinwell process has produced active n- and p-channel FET’s with excellent characteristics such as low threshold voltage, low subthreshold swing, and high transconductance.
Phan, Linh V.
"Fabrication of Twin-well CMOS,"
Journal of the Microelectronic Engineering Conference: Vol. 7
, Article 8.
Available at: http://scholarworks.rit.edu/ritamec/vol7/iss1/8