An NPN bipolar transistor process was designed and fabricated for incorporation with RIT’s N well CMOS technology to develop BiCMOS devices. The only additions to the CMOS process were the base masking step, base implant, and drive. Base dose was varied to achieve current gains of 50, 100, and 200 using SUPREM-3. Unfortunately, do to an incomplete etch of the collector region, a rework had to be performed, whose added temperature steps pushed the emitter through the base.
Ternullo, Luigi Jr
"Bipolar Device Fabrication Using RIT's CMOS Technology to Develop a BICMOS Process,"
Journal of the Microelectronic Engineering Conference: Vol. 5
, Article 24.
Available at: http://scholarworks.rit.edu/ritamec/vol5/iss1/24