Publication Date
1990
Document Type
Paper
Abstract
Two 2” Gallium Arsenide wafers underwent MBE deposition processing to create two differing epitaxial layer schemes for processing of MESFET devices. ~ four level process was used to fabricate isolated MESFET structures, diodes, resistors, other test structures, and simple logic gates using Buffered FET Logic (BFL). Two ohmic contact schemes were utilized; Aluminum for an as-deposited contact to InGaAs and AuGe as an alloyed contact to Gags. Results were working MESFETs with pinchoff voltages ranging from -lv to -4V, source to drain saturation currents ranging from 7 to 28 mP~, and transconductances up to 22.4 milliSiemens. Schottky C-V and interdigitated diodes had threshold voltages of 0.4 to 0.6 volts. Logic reliability, however, was very low, with few gates functional.
Recommended Citation
Petzold, Dave
(1990)
"GaAs MESFET Logic,"
Journal of the Microelectronic Engineering Conference: Vol. 4:
Iss.
1, Article 27.
Available at:
https://repository.rit.edu/ritamec/vol4/iss1/27