A Static Random Access Memory (SRAM) was designed using a 2 micron minimum geometry, nMOS fabrication process on an Apollo design station. In addition to the SRAN integrated circuit, test structures were included to help characterize the process and design. The chip contained over 200 transistors on a die size of 800 square microns. Simulation results predicted an access time of 50 nano—seconds. The pads were configured to fit a 20 pin probe card to facilitate automatic testing.
Dougherty, David W.
"16 x 1 nMOS Static Random Access Memory Design,"
Journal of the Microelectronic Engineering Conference: Vol. 2
, Article 9.
Available at: http://scholarworks.rit.edu/ritamec/vol2/iss1/9