Publication Date
2009
Document Type
Paper
Abstract
Esaki diodes are tunnel diodes with a very abrupt and degenerately doped PN junction. This abrupt junction causes the conduction bands to overlap, thus allowing for tunneling when a small bias is applied. 111-V on silicon Esaki tunnel diodes offer higher performance at lower power supplies compared to silicon. A vertical mesa etch is used to isolate the Esaki devices from each other. The etch results in a significant undercut below the gold contact which can cause issues with electrical testing. When probed the gold contact can short to the substrate. The solution to this is the addition of a dielectric layer around the tunnel diode. The dielectric layer will reduce the topography variation caused by the mesa etch and prevent the metal contact from shorting to the surface. Bisbenzocyclobutene (BCB) is a spin on polyimide with a low dielectric constant (k = 2.5) and a high degree of planarization.
The development of BCB planarization process allows for better electrical testing of the Esaki diodes. Further, this BCB planarization process can be incorporated into e-beam lithography process and utilized in the fabrication of Tunneling Field Effect Transistors (TFET) and Heterojunction Bipolar Transistors.
Recommended Citation
Barth, Michael J.
(2009)
"Development of a Planarization Process for the Fabrication of III-V on Silicon Esaki diodes,"
Journal of the Microelectronic Engineering Conference: Vol. 18:
Iss.
1, Article 1.
Available at:
https://repository.rit.edu/ritamec/vol18/iss1/1