A successful test layout for S-parameter analysis was demonstrated. Process characterization accomplished as part of this project demonstrated a pseudo-shallow trench isolation. Active device measurements would have been possible with a DC blocking fixture. 0.37 μm-I.0 μm transistors were fabricated with a non-ideal characteristic which i~as due to the source drain implant being blocked by oxide residue from the spacer formation etch.
James, Adam L.
"NMOS Transistors Design and Fabrication for S-Parameter Extraction,"
Journal of the Microelectronic Engineering Conference: Vol. 15
, Article 2.
Available at: http://scholarworks.rit.edu/ritamec/vol15/iss1/2