Advancing RIT to Submicron Technology: Design and Fabrication of 0.5μm N-channel MOS Transistors

Authors

Michael Aquilino

Publication Date

2003

Document Type

Paper

Abstract

The design and fabrication of N-channel MOS transistors with effective gate lengths of 0.5μm or smaller have been completed at the Semiconductor and Microsystems Fabrication Laboratory at the Rochester Institute of Technology. An NMOS device with L_mask = 0.7μm results in an L_eff= 0.5μm. The drive current for this device with supply voltage of 3.5V is 108μA/μm. The sub-threshold slope is 100mV/decade and a DIBL parameter of 29mV/V is reported. An NMOS device withL_mask=0.6μm results in an L_eff =0.4μm. The drive current for this device with supply voltage of 3.5V is l40μA/μm. The sub-threshold slope is 103mV/decade and a DIBL parameter of 11OmV/V is reported. These are RIT’s first sub-0.5micron MOS transistors.

Recommended Citation

Aquilino, Michael (2003) "Advancing RIT to Submicron Technology: Design and Fabrication of 0.5μm N-channel MOS Transistors," Journal of the Microelectronic Engineering Conference: Vol. 14: Iss. 1, Article 1.
Available at: https://repository.rit.edu/ritamec/vol14/iss1/1