Design, Fabrication, and Testing of Crystalline Silicon source/ Drain FinFETs

Authors

Jesse J. Siman

Publication Date

2002

Document Type

Paper

Abstract

Crystalline silicon source/drain FInFET structures were designed, fabricated, and tested at the RIT Semiconductor & Microsystems Fabrication Laboratory (SMFL). Process development was completed using hand calculations, simulations, and similar processing techniques based upon mature RIT semiconductor manufacturing processes. The design under investigation is a dog-bone structure fabricated on SOT substrates. The crystalline silicon source/drain FinFETs exhibited a field effect behavior for all transistor sizes fabricated, however the smaller 1μm FinFETs were more susceptible to background noise. The smallest device, a 1x2μm FInFET yielded V_T=1.53V and a drive current of 510 μA with V_G=5V. The largest device, a 4x80μm FinFET yielded V_T=1.42V and a drive current of 4.1 mA with V_G=SV..

Recommended Citation

Siman, Jesse J. (2002) "Design, Fabrication, and Testing of Crystalline Silicon source/ Drain FinFETs," Journal of the Microelectronic Engineering Conference: Vol. 12: Iss. 1, Article 5.
Available at: https://repository.rit.edu/ritamec/vol12/iss1/5