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Publication Date

2000

Document Type

Paper

Abstract

Silicon based ring gate surface junction tunneling devices (SJT) were studied due to their promise of incorporating quantum functional devices with integrated circuits. SJT devices of various gate lengths ranging from 1 μm to 50 μm were designed using Mentor Graphics tools, and were fabricated using standard CMOS processes on S1MOX substrates. SIMOX wafers were used to help reduce bulk leakage and enhance the drain impurity profile. SIMOX mesa isolation also significantly reduced the process flow.

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