To allow for a quicker, more efficient design process, a PMOS standard cell library has been designed. The cells designed include; NAND, AND, OR, NOR and Exclusive OR gates, Output Pad Driver, RS Flip-Flop, D-type Flip-Flop, Shift Register, Up-Down Counter, Multiplexor, Decoder, Encoder, Inverter, and a Serial Adder. These cells were all simulated using SPICE, and laid out with ten micron metal gate PMOS design rules.
Taylor, James C.
"PMOS Standard Cell Library,"
Journal of the Microelectronic Engineering Conference: Vol. 1
, Article 31.
Available at: https://scholarworks.rit.edu/ritamec/vol1/iss1/31