This paper reports a concept to design the defect-tolerant molecular integrated circuits (MICs). The results are applicable to conventional ICs which utilize solid-state devices. By enhancing photolithography and other CMOS processes, advancing materials and optimizing devices, some device and circuit performance were improved. Unfortunately, some key performance characteristics and capabilities were significantly degraded. The performance tradeoffs and effects of the equivalent cell size reduction are well known. The defects and faults at the device and circuit levels must be accommodated. It is illustrated that in general, the defects and faults can be accommodated.

Date of creation, presentation, or exhibit



Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. ISBN: 978-1-4244-2103-9Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Microelectronic Engineering (KGCOE)


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