A number of SRAM-based field programmable gate arrays (FPGAs) allow for partial reconfiguration (PR). Partial reconfiguration can be used to maximize the resource utilization in these FPGAs. Current methodologies use both external and self partial reconfiguration for this purpose. On mature multichip (MC) systems that have not made use of the PR features of their SRAM-based FPGA(s), however, these methodologies would require changes in the existing FPGA configuration protocol and/or associated hardware outside the array. This paper presents a novel methodology that makes PR features available to these systems for the purpose of maximizing their FPGA resources without the modifications required by the current methodologies. The proposed methodology reuses an existing data interface to send the PR data to the array and directs this data to the FPGA’s internal configuration port. A prototype of this methodology is demonstrated on a commercial color space conversion (CSC) engine design using two Xilinx Virtex-II Pro FPGAs.

Date of creation, presentation, or exhibit



Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs, 2008 Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Microelectronic Engineering (KGCOE)


RIT – Main Campus