This paper presents a design methodology for implementing the HD photo compression algorithm within a FPGA. The HD photo compression algorithm is comprised of five pipelined functional stages; (transformation, quantization, prediction, scanning, and encoding) some of which can be manipulated to obtain a lower cost and/or higher performance solution. This flexibility enables tailored solutions to be developed for a broader spectrum of applications. An Altera Stratix III FPGA can compress a 56 megapixel image in hundreds of microseconds.

Date of creation, presentation, or exhibit



This paper appears in: SOC Conference, 2008 IEEE International held on September 17-20, 2008, pps. 105-108 ©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Computer Engineering (KGCOE)


RIT – Main Campus