This paper presents a 5.46 mW H.264/AVC Video Stream Parser implemented in 65nm. The differences between targeting a video stream parser architecture for a 65nm CMOS ASIC and a Virtex 5 FPGA are also compared. Overall, the ASIC implementations showed higher performance and lower area than an FPGA, with a 600/0 increase in performance and 6x decrease in area.
Date of creation, presentation, or exhibit
Department, Program, or Center
Computer Engineering (KGCOE)
Brown, Michelle and Hsu, Kenneth, "A Novel 5.46 mW H.264/AVC video stream parser IC" (2008). Accessed from
RIT – Main Campus