Description

This paper presents a 5.46 mW H.264/AVC Video Stream Parser implemented in 65nm. The differences between targeting a video stream parser architecture for a 65nm CMOS ASIC and a Virtex 5 FPGA are also compared. Overall, the ASIC implementations showed higher performance and lower area than an FPGA, with a 600/0 increase in performance and 6x decrease in area.

Date of creation, presentation, or exhibit

2008

Comments

This paper appears in: SOC Conference, 2008 IEEE International. Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Computer Engineering (KGCOE)

Campus

RIT – Main Campus

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