Description

Low-power quantization architecture for H.264/AVC is presented and implemented on VLSI. The multiplication operation is replaced with shifts and additions. Similar designs were proposed which had 75.2% area and 76.30/0 power on average saved compared with original H.264 quantization scheme, along with an error percent within 6.4% range. In this paper, the improved architecture has error percent within 2.4% range. The power and area saved on average is -8% compared to designs of similar architecture.

Date of creation, presentation, or exhibit

2008

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Computer Engineering (KGCOE)

Campus

RIT – Main Campus

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