Low-power quantization architecture for H.264/AVC is presented and implemented on VLSI. The multiplication operation is replaced with shifts and additions. Similar designs were proposed which had 75.2% area and 76.30/0 power on average saved compared with original H.264 quantization scheme, along with an error percent within 6.4% range. In this paper, the improved architecture has error percent within 2.4% range. The power and area saved on average is -8% compared to designs of similar architecture.
Date of creation, presentation, or exhibit
Department, Program, or Center
Computer Engineering (KGCOE)
Michael Michael and Kenneth Hsu "A Low-power Design of Quantization for H.264 Video Coding Standard," Proceedings of the IEEE International SOC Conference, Newport Beach, CA, September 17-20, 2008, Pp. 201-204
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