With rapid scaling of CMOS technology, subthreshold and gate leakage mechanisms have become dominant. With feature size scaling beyond 50nm, gate leakage has become comparable to subthreshold leakage. In such a scenario, gate leakage currents can no longer be ignored in NMOS devices that are switched OFF. Previous studies on gate leakage current do not consider the effect of this component. In this paper, we study the interdependence between subthreshold and gate current by including gate current in OFF transistors and estimate minimum leakage input vectors. Performing analysis on fundamental CMOS combinational and sequential blocks has shown that the gate leakage current in OFF transistors has a significant impact on the total leakage current to the extent that the minimum leakage vectors are no longer the same when this particular leakage component is considered. Based on the factors affecting subthreshold and gate leakage currents and their interdependence, different scenarios are identified which are used in minimum leakage vector pattern estimation. In the case of stacks with variable number of transistors, a standard approach is developed in determining minimum leakage vectors.

Date of creation, presentation, or exhibit



Proceedings o the IEEE Midwest Symposium on Circuits and Systems 2007, Montreal, Canada. August 2007. Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Computer Engineering (KGCOE)


RIT – Main Campus