The Computer Architecture course at the Rochester Institute of Technology (RIT) is taken by undergraduate students in their fourth year of study, after they have had an Introduction to Digital Systems, to Programming in C, and to Microprocessor Programming. The course gives students the computer hardware designer’s perspective, with an emphasis on complete logic design. The objective of the laboratory is the design, simulation and implementation of a processor in a reconfigurable hardware device. Each weekly laboratory assignment builds upon the previous one. The bottom-top design process starts with the design of a combinational logic Arithmetic and Logic Unit, of a Register File and Memory Blocks. The design of the Central Processing Unit is divided into the design of the Data Path and Control Unit. The Instruction Set Architecture is enforced, i.e. the students do not have to come up with their own instruction set. All students must follow general and individual design specifications. The latter are selected using a binary code assigned to each student. The value of each bit chooses between design alternatives such as: Von-Neumann versus Harvard, I/O Mapped versus Memory Mapped Peripherals, 3-bus versus 2-bus architecture, tri-state versus multiplexer data transfer, hardwired versus microprogrammed control unit etc. Each final processor implementation is different from any other, but can run the same machine code. The paper presents the organization of the laboratory sequence, describes each weekly assignment and the lessons

Date of creation, presentation, or exhibit



Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Electrical, Computer and Telecommunications Engineering Technology (CAST)


RIT – Main Campus