Efficient use of R&D laboratory resources including fabrication and metrology tools, analytical equipment, and operators and technicians is critical to product development, time to market, and ultimately company success. Capacity and productivity modeling in R&D fabs presents significant challenges and is not usually well understood. Simulation modeling can provide an accurate representation of the R&D fab that can be used to investigate the operational aspects of the fab and provide a quantitative statistical analysis of Jab performance measures. A simulation study of the Semiconductor & Microsystems Fabrication Laboratory (SMFL) al the Rochester Institute of Technology (RlT) is used to present a case study on this methodology. A baseline CMOS process is used as the representative product load, which accounts for the variety of research activities in progress in the SMFL. The fab performance is assessed by the cycle time, WIP, and throughput of representative load lots.

Date of creation, presentation, or exhibit



In the Proceedings of the 2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Piscataway, New Jersey, pp. 157-161, May 2004 Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Industrial and Systems Engineering (KGCOE)


RIT – Main Campus