Power consumption in state-of-the-art embedded systems is determined to a large extent by on-chip caches. In these systems, technology scaling has resulted in an increase of subthreshold and gate leakage currents, which contribute significantly to the total cache power consumption. This underlines a need to analyze leakage power consumption and control techniques at every level of system design in embedded applications. In this paper, we have studied three individual leakage control techniques using Hotleakage [2], applied at architectural level over a range of smaller technology sizes including 70nm. Specifically, evaluation of the effects of varying L1 cache sizes (with the size of the other cache constant) demonstrated that the leakage power is directly proportional to the size of the L1 cache. With increasing L2 cache sizes the leakage power increased almost to -50% of the total L2-cache power consumption for 70nm technology.

Date of creation, presentation, or exhibit



Proceedings 47th IEEE International Midwest Symposium on Circuits and Systems, July, 2004. Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Computer Engineering (KGCOE)


RIT – Main Campus