The pipelined interconnect free (PIF) logic is a novel design paradigm shift that has the potential of eliminating several problems that are currently constraining the digital design community. Since interconnects, and not gates have become the bottleneck in deep sub-micron technology, it makes sense to find an alternative to today's interconnects. We propose to replace interconnects of non-adjacent gate cells with chains of gates. However, the new type of design is more than a mere replacement of interconnects with gates. As demonstrated with a PIF logic based 64 bit adder example, the new design becomes a well-structured design with predictable delays. In contrast, in a conventional design, lack of accurate interconnect delay values force more pessimistic constraints to be applied to the design.
Date of creation, presentation, or exhibit
Department, Program, or Center
Microelectronic Engineering (KGCOE)
Retanubun, Richard; Patru, Dorin; and Mukund, P.R., "Pipelined interconnect free logic" (2003). Accessed from
RIT – Main Campus