Description

The pipelined interconnect free (PIF) logic is a novel design paradigm shift that has the potential of eliminating several problems that are currently constraining the digital design community. Since interconnects, and not gates have become the bottleneck in deep sub-micron technology, it makes sense to find an alternative to today's interconnects. We propose to replace interconnects of non-adjacent gate cells with chains of gates. However, the new type of design is more than a mere replacement of interconnects with gates. As demonstrated with a PIF logic based 64 bit adder example, the new design becomes a well-structured design with predictable delays. In contrast, in a conventional design, lack of accurate interconnect delay values force more pessimistic constraints to be applied to the design.

Date of creation, presentation, or exhibit

2003

Comments

Copyright 2003 IEEE Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. ISBN: 0-7803-8182-3Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Campus

RIT – Main Campus

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