The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (Jp) of 188 A/cm2 whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with Jp of 278 A/cm2. Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and Jp of 332 A/cm2. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.
Date of creation, presentation, or exhibit
Department, Program, or Center
Microelectronic Engineering (KGCOE)
Sudirgo, Stephen; Curanovic, Branislav; Rommel, Sean; and Hirschman, Karl, "Challenges in integration of resonant interband tunnel devices with CMOS" (2003). Accessed from
RIT – Main Campus