In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as self-resetting or delayed-reset domino circuits used in IBM's gigahertz processor (GUTS) and asynchronous circuits used in Intel's RAPPID instruction length decoder. These new timed circuit styles, however, cannot be efficiently and accurately analyzed using traditional static timing analysis methods. This lack of efficient analysis tools is one of the reasons for the lack of mainstream acceptance of these design styles. This paper discusses several industrial timed circuits and gives an overview of our timed circuit design methodology.
Date of creation, presentation, or exhibit
Department, Program, or Center
Microelectronic Engineering (KGCOE)
Myers, Chris; Belluomini, Wendy; Killpack, Kip; and Mercer, Eric, "Timed circuits: A New paradigm for high-speed design" (2001). Accessed from
RIT – Main Campus