With the immense size of images, compression has become a common way of minimizing the amount of storage necessary for images. This is also beneficial for transmission purposes. The Joint Photographic Experts Group (JPEG) standard is frequently used for still images. This standard is very flexible and many of the same algorithms can be used for video applications. Video applications require large amounts of data to be processed every second. Therefore, the following describes the hardware design of a chip allowing for high-speed compression. The design uses the JPEG algorithms and is targeted towards ASIC design. Further plans include use of field programmable gate arrays (FPGAs). The hardware design is based on grayscale images and only works with the raw image data.

Date of creation, presentation, or exhibit



Proceedings of the SPIE Conference on Input/Output and Imaging Technologies , ppp 281-292, July 1998 Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Computer Engineering (KGCOE)


RIT – Main Campus