Description

Priority arbitration is an essential part of the ATM switches in order to support the integration of telecommunication services with difference characteristics. Service priority control selects the connection to output a cell among all connections destined to the same output port. Discard priority contral selects the connection to discard a cell when the shared buffer is full. In this paper we present a VLSI design of a priority arbitrator for shared buffer ATM switches. This priority arbitrator is targeted to support our new service priority control scheme, reactive bandwidth arbitration (RBA), and new discard priority control scheme, local pushout discarding (LPD). The priority arbitrator is designed for an 8x8 shared buffer ATM switch with four priority classes per port and a link rate of 622 Mbps. The chip has 130k gates in a chip area of B7.88 mm2 using 0.6 micrometers CMOS technology.

Date of creation, presentation, or exhibit

1997

Comments

Proceedings of IEEE International Symposium on Circuits and Systems, vol. 4, pp. 2785-2788, 1997 Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type

Conference Proceeding

Department, Program, or Center

Computer Engineering (KGCOE)

Campus

RIT – Main Campus

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