The JPEG-LS algorithm is one of the recently designated standards for lossless compression of grayscale and color images. Simulation results for lossless and near lossless compression of various image types are presented in order to explore the algorithm's effectiveness for a number of applications. A hardware implementation using VHDL is proposed and the schematic of a JPEG-LS codec, that is capable of standard-compliant lossless and near lossless encoding and decoding, has been generated using the Synopsys synthesis tool. Hardware implementation of the proposed solution on an FPGA allows for real-time processing of large image volumes.

Publication Date



" Benchmarking and hardware implementation of JPEG-LS," Proceedings of the 2002 International Conference on Image Processing. The Institute for Electrical and Electronics Engineers (IEEE). Held in Septmeber, 2002. ©2002 Institute of Electrical and Electronics Engineers (IEEE). Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.ISBN:0-7803-7622-6 ISSN:1522-4880 Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works in February 2014.

Document Type


Department, Program, or Center

Chester F. Carlson Center for Imaging Science (COS)


RIT – Main Campus